1. Field of the Invention
The present invention relates to a NAND flash memory using, e.g., an EEPROM, and more particularly to a semiconductor memory device capable of storing multivalued data in a single memory cell.
2. Description of the Related Art
In a NAND flash memory, a plurality of memory cells arranged in a column direction are connected in series to constitute a NAND cell, and each NAND cell is connected with a corresponding bit line through a select gate. Each bit line is connected with a latch circuit which latches write data and read data. There has been proposed a non-volatile semiconductor memory device capable of storing multivalued data in this NAND flash memory (see, e.g., Jpn. Pat. Appln. KOKAI Publication No. 2000-195280).
In recent years, miniaturization of an element has advanced, and a distance between cells is decreasing. Therefore, an influence of a floating gate capacity between cells adjacent to each other is becoming large. Specifically, there has arisen a problem that a threshold voltage of a cell in which data has been previously written fluctuates due to a threshold voltage of a cell which is adjacent to the former cell and in which data is subsequently written. In particular, since a multivalued memory which stores a plurality of sets of data each consisting of two or more bits in a single cell stores a plurality of sets of data by using a plurality of threshold voltages, a distribution of a threshold voltage corresponding to one set of data must be controlled to be extremely narrowed. Therefore, the influence of the threshold voltage of the adjacent cell is prominent.
In order to solve this problem, in a memory cell in which one-bit (a first page) data is stored, one-bit (the first page) data is written in an adjacent memory cell to reach a threshold voltage (a V-level) lower than an original threshold voltage before storing the next data. After writing the data in this adjacent memory cell, writing to increase the voltage to the original threshold voltage (a word line potential “b” (V<=B)) is carried out in writing a second page. However, it is hard to recognize that data of the first page has been written with to the original threshold voltage or the lower threshold voltage before and after writing the second page. Therefore, in order to recognize this, there has been proposed a write scheme by which a flag memory cell (which will be referred to as a flag cell) is prepared in accordance with each page and a read operation is performed in accordance with data in this flag cell (see, e.g., Jpn. Pat. Appln. KOKAI Publication No. 2004-192789).
In a case where data of the second page is written based on this write scheme, when data of the first page is “1” and data of the second page is “0”, data in the memory cell is changed from “0” to “1”, a threshold voltage is increased to, e.g., a level A. Further, when data of the first page is “0”, its threshold voltage is determined as a voltage including the level A. Therefore, their threshold voltage distributions overlap each other. Therefore, when writing is interrupted due to, e.g., an abnormal cutoff of a power supply during writing the second page, there occurs a problem that the previously written first page data is also destroyed. Therefore, there has been demanded a semiconductor memory device which can avoid destruction of data of the first page even if writing the second page is abnormally interrupted.